The phase locked loop (PLL) has been widely used in communication applications. PLLs have been used to recover a signal from a noisy communication channel, generate a stable frequency at multiples of an input frequency, and for demodulating a signal. FIG. 1 is an example of a PLL block diagram. The PLL 100 includes a phase detector (PD) 105, loop filter (LF) 110, and voltage controlled oscillator (VCO) 115. The phase detector 105 compares the phase of a periodic input signal against the phase of the VCO 115 signal; the output of the PD 105 is a measure of the phase error between its two inputs. The error voltage is then filtered by the loop filter 110, whose output is a control voltage that is applied to the VCO 115.
The control voltage changes the VCO frequency in a direction that reduces the phase error between the input signal and the VCO. When the loop is locked, the control voltage sets the average frequency of the VCO to be the same as the average frequency of the input signal. Traditionally, the integrated on-chip voltage controlled oscillator (VCO) has been implemented as L-C tank circuitry. Due to low Q of the on-chip inductor, the VCO phase noise may be limited. An off-chip high Q device such as a crystal may be used as a reference to reduce the overall phase noise of the output.